Although silicon gate semiconductor devices heretofore have been provided, the fabrication process has been excessively complex, larger wafer areas have been required, and multiple physical step heights have been required in the wafer topography. There is a need for an MOS semiconductor device of reduced size and having fewer physical step heights and improved yields. Further there is a need for simplifying the processing steps to achieve fewer physical step heights and reducing the number of masking and other processing steps.